Pilot contamination problem arises by reusing the same set of pilots in different cells

What is Pilot Contamination in Massive MIMO?

5G NR standard supports both Frequency Division Duplex (FDD) and Time Division Duplex (TDD) modes in massive MIMO systems. For a reasonably pure estimate, it is necessary to make sure that each pilot transmission in a cell occurs in a vacuum, i.e., free from the interference of other pilots in the same time or frequency. This is achieved through orthogonality or separation of training signals in time or frequency slots. As we see now, simple orthogonality is not enough and new problems emerge due to the interaction among different cells in a network. Uplink A set of orthogonal pilots in

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Average trajectory for squared eye diagrams for a binary PAM sequence of 400 symbols shaped with Raised Cosine pulse with excess bandwidths 0, 0.5 and 1

Lock Detectors for Symbol Timing Synchronization

Similar to the carrier lock detectors, timing lock detectors can also be constructed based on some property of the modulated signal. These lock detectors operate in parallel to the timing locked loop and aid the Rx state machine in executing necessary tasks according to each scenario. The expressions for two such timing lock detectors are as follows. The output of a timing lock detector should be at its peak for the correct timing. Therefore, when the matched filter output, denoted by $z(mT_M)$ with $T_M$ being the symbol time, is at its peak, the second sample in a signal oversampled by

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A discrete-time PLL with a PI loop filter and an NCO consisting of a phase accumulator and a Look-Up Table (LUT)

Phase Locked Loop (PLL) in a Software Defined Radio (SDR)

IBM Watson and Google DeepMind are the most complex computers that, some believe, will try to run the world in a distant future. A PLL on the other hand is the simplest computer that actually runs so much of the world as a fundamental component of intelligent electronic circuits. The PLL was invented by the French engineer Henri de Bellescize in 1932 when he published his first implementation in the French journal L’Onde Electrique. A Phase Locked Loop (PLL) is a device used to synchronize a periodic waveform with a reference periodic waveform. In essence, it is an automatic control

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S-curve for decision-directed maximum likelihood phase error detector

What are Cycle Slips and Hangup in Phase Locked Loops?

In a previous article, we have covered in detail the inner workings of a Phase Locked Loop (PLL) in a Software Defined Radio (SDR). There are two phenomena that have the potential to occasionally disrupt the performance of a PLL operating in steady state: cycle slips and hangup. Both the carrier and timing locked loops suffer from these issues. The underlying mathematics is quite intricate and hence I give a simple overview of these concepts. A reader interested in further exploration is referred to [1]. Cycle Slips To understand the cycle slip, assume that the loop is in tracking mode,

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