Square-Root Raised Cosine Archives | Page 2 of 2

Illustration of peak ISI and asymmetry about -3dB point

July 18, 2016 DSP / Wireless/SDR

Pulse Shaping Filter

In digital logic, a stream of 1s and 0s forms a sequence of rectangular pulses, which can be easily identified at the receiver side by a threshold. In time domain, everything looks nice and perfect. Let us investigate the system characteristics in frequency domain. In a Pulse Amplitude Modulation (PAM) system, the main component that defines the spectral contents of the signal is the pulse shape $p(nT_S)$ at the Tx. We start with our attention towards a simple rectangular pulse shape. Here is a brief outline of what we cover in this article. Table of Contents 1. Spectrum of a

Minimum distance rule based detector decisions in a QPSK constellation in the presence of a carrier frequency offset

June 6, 2016 DSP / Wireless/SDR

How a Frequency Locked Loop (FLL) Works

We saw before how a carrier frequency offset distorts the received signal. Later, we also described the classification of frequency synchronization techniques according to the availability of the symbol timing. Today, we will learn about the workings of a frequency locked loop. Background A Phase Locked Loop (PLL) is a device used to synchronize a periodic waveform with a reference periodic waveform. It is an automatic control system in which the phase of the output signal is locked to the phase of the input reference signal. In the article referred above, we also discussed that for a very small frequency