## Why Building an SDR Requires DSP Expertise

In an introduction to signals, we discussed the idea that the any activities around us, starting from subatomic particles to massive societal networks, are generating signals all the time. Since mathematics is the language of the universe and digital signals are nothing but quantized number sequences, it is fair to say that the workings of the universe can be mapped to an infinitely large set of signals. With these number sequences in hand, an electronic computer can process the signals and either extract the information about the surrounding real world phenomena or even better influence its target environment. We saw

## Maximum Likelihood Sequence Estimation (MLSE Equalizer)

In the discussion on a wireless channel, we saw that an increased amount of Inter-Symbol Interference (ISI) occurs for high data-rate wireless systems that impacts the system performance to a significant extent. The performance of a linear equalizer suffers from spectral nulls. A Decision Feedback Equalizer (DFE) recovers much of the performance losses due to ISI but it is susceptible to error propagation. In 1972, David Forney published a paper titled "Maximum-likelihood sequence estimation of digital sequences in the presence of intersymbol interference" in which he proposed the idea of sequence estimation. For this purpose, there was an implicit assumption

We have discussed before the distortion caused by a symbol timing offset on the communication waveform. We have also derived a maximum likelihood estimate of the clock phase offset. In this article, we describe the impact of a sampling clock offset in a single-carrier waveform, also commonly known as a clock frequency offset or timing drift. A clock frequency offset is defined as the rate mismatch between the Tx and Rx clocks. Just like a carrier phase and frequency offset, the clock used to sample the incoming continuous-time signal at a rate $T_S=1/F_S$ contains a phase and frequency offset as