Wireless/SDR Archives | Page 19 of 22

An illustration of wiping off the modulation process without any training information

August 11, 2016 Wireless/SDR

Non-Data-Aided Carrier Phase Estimation

A carrier phase offset rotates the Rx constellation causing decision errors even in a perfectly noiseless environment. One of the techniques used to overcome this problem is to insert a known sequence at the start of the transmission known as a preamble. Then, the Rx can utilize these known symbols in the arriving signal to estimate the carrier phase and de-rotate the constellation. However, inserting a known sequence within the message decreases the spectral efficiency of the system. To avoid this cost, a phase estimator (as well as estimators for other distortions) can be derived in a non-data-aided fashion. One

Square-Root Raised Cosine (SR-RC) spectrum with different excess bandwidths

August 7, 2016 Wireless/SDR

Modulation Bandwidths

From the article on pulse shaping, we can correctly determine the occupied bandwidth for each modulation scheme where the Square-Root Raised Cosine spectrum shows the bandwidth of a Square-Root Raised Cosine pulse shape as $0.5(1+\alpha)R_M$. Also, we have discussed earlier that the spectrum approximately remains the same, provided that there is enough randomness in bit stream and the resulting symbols are equally likely and independent from each other. Therefore, the bandwidth for a PAM modulated signal can be given as \begin{equation}\label{eqCommSystemBWPAM} BW_{\text{PAM}} = 0.5\left(1+\alpha\right)R_M \end{equation} QAM is basically a similar modulation scheme except that it is modulated on a carrier.

A Phase Locked Loop (PLL) for digital symbol timing recovery

August 3, 2016 Wireless/SDR

Phase Locked Loop (PLL) for Symbol Timing Recovery

A Phase Locked Loop (PLL) is a device used to synchronize a periodic waveform with a reference periodic waveform. It is an automatic control system in which the phase of the output signal is locked to the phase of the input reference signal. In the context of carrier phase synchronization, we talk about tracking the phase of an input reference sinusoid. For carrier frequency synchronization, a Frequency Locked Loop (FLL) is implemented. For the purpose of timing synchronization, the target is to adjust the timing phase of a receiver clock to that of the transmitter clock such that one sample/symbol

A channel with 8 taps demonstrating the main cursor, precursor ISI and postcursor ISI

January 31, 2022 Wireless/SDR

How Decision Feedback Equalizers (DFE) Work

We started the classification of equalization algorithms by introducing the need for equalization in wireless communication systems. We said that the wireless channel is a source of severe distortion in the received (Rx) signal and our main task is to remove the resulting Inter-Symbol Interference (ISI) from the Rx samples. Equalization refers to any signal processing technique in general and filtering in particular that is designed to eliminate or reduce this ISI before symbol detection. In essence, the output of an equalizer should be a Nyquist pulse for a single symbol case. A conceptual block diagram of the equalization process

Block diagram of a 4 symbol communication system

August 1, 2016 Wireless/SDR

Packing More Bits in One Symbol

Note that digital electronics are constrained to work on only two levels by electronic switches which in the simplest case are either on or off. For many reasons, practical digital communication systems require quite complicated signal processing workload both at the Tx and Rx ends that can be performed only by a device more intelligent than an electronic switch, such as an Application Specific Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA), Digital Signal Processor (DSP) or a General Purpose Processor (GPP). If this intelligent device can differentiate between two signal levels like a switch, it can certainly differentiate between