Tag: Phase Locked Lop (PLL)

A matched filter in continuous frequency domain along with the corresponding frequency matched filter for excess bandwidth 0.25
DSP / Wireless/SDR

Band Edge Filters for Carrier and Timing Synchronization

Band edge filters for carrier frequency and symbol timing synchronization is a very interesting topic that elegantly relates the tool (DSP) to the application (SDR design). This article is a short summary of where they originate from and what role they play for synchronization purpose. A Carrier Frequency Offset (CFO) arises due to a mismatch between Tx and Rx local oscillators as well as a phenomenon known as Doppler effect. In some other articles on this website, you will also find information on the Phase Locked Loop (PLL) in the context of carrier phase and timing synchronization. There is another

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An illustration of wiping off the modulation process without any training information
Wireless/SDR

Non-Data-Aided Carrier Phase Estimation

A carrier phase offset rotates the Rx constellation causing decision errors even in a perfectly noiseless environment. One of the techniques used to overcome this problem is to insert a known sequence at the start of the transmission known as a preamble. Then, the Rx can utilize these known symbols in the arriving signal to estimate the carrier phase and de-rotate the constellation. However, inserting a known sequence within the message decreases the spectral efficiency of the system. To avoid this cost, a phase estimator (as well as estimators for other distortions) can be derived in a non-data-aided fashion. One

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A BPSK constellation in a the presence of a carrier phase offset. A hypothetical QPSK constellation is also shown for comparison
Wireless/SDR

How to Detect a Carrier Lock in an SDR

We have discussed before the effect of a phase offset on the received signal. We have also seen a logical approach to solve this problem as well as one of the earliest algorithms for phase synchronization known as a Costas loop. Here, the purpose is to explain how a Rx detects whether the Phase Locked Loop (PLL) has acquired the lock. A receiver is simply a blind machine which can implement a PLL but can never get to know how it is actually doing. A lock detector is a logic signal used in the Rx to indicate successful synchronization after

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Minimum distance rule based detector decisions in a QPSK constellation in the presence of a carrier frequency offset
DSP / Wireless/SDR

How a Frequency Locked Loop (FLL) Works

We saw before how a carrier frequency offset distorts the received signal. Later, we also described the classification of frequency synchronization techniques according to the availability of the symbol timing. Today, we will learn about the workings of a frequency locked loop. Background A Phase Locked Loop (PLL) is a device used to synchronize a periodic waveform with a reference periodic waveform. It is an automatic control system in which the phase of the output signal is locked to the phase of the input reference signal. In the article referred above, we also discussed that for a very small frequency

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