We have discussed before the distortion caused by a symbol timing offset on the communication waveform. We have also derived a maximum likelihood estimate of the clock phase offset. In this article, we describe the impact of a sampling clock offset in a single-carrier waveform, also commonly known as a clock frequency offset or timing drift. A clock frequency offset is defined as the rate mismatch between the Tx and Rx clocks. Just like a carrier phase and frequency offset, the clock used to sample the incoming continuous-time signal at a rate $T_S=1/F_S$ contains a phase and frequency offset as
Continue reading![Due to a Sampling Clock Offset (SCO), a fast Rx clock collects extra samples](https://wirelesspi.com/wp-content/uploads/2022/01/figure-timing-sync-negative-sampling-clock-offset.png)