Synchronization Archives | Page 4 of 4

An illustration of wiping off the modulation process without any training information

August 11, 2016 Wireless/SDR

Non-Data-Aided Carrier Phase Estimation

A carrier phase offset rotates the Rx constellation causing decision errors even in a perfectly noiseless environment. One of the techniques used to overcome this problem is to insert a known sequence at the start of the transmission known as a preamble. Then, the Rx can utilize these known symbols in the arriving signal to estimate the carrier phase and de-rotate the constellation. However, inserting a known sequence within the message decreases the spectral efficiency of the system. To avoid this cost, a phase estimator (as well as estimators for other distortions) can be derived in a non-data-aided fashion. One

A BPSK constellation in a the presence of a carrier phase offset. A hypothetical QPSK constellation is also shown for comparison

July 23, 2016 Wireless/SDR

How to Detect a Carrier Lock in an SDR

We have discussed before the effect of a phase offset on the received signal. We have also seen a logical approach to solve this problem as well as one of the earliest algorithms for phase synchronization known as a Costas loop. Here, the purpose is to explain how a Rx detects whether the Phase Locked Loop (PLL) has acquired the lock. A receiver is simply a blind machine which can implement a PLL but can never get to know how it is actually doing. A lock detector is a logic signal used in the Rx to indicate successful synchronization after

July 9, 2016 DSP / Wireless/SDR

Digital Filter and Square Timing Recovery

We have seen before how a symbol timing offset severely impacts the constellation of the received symbols. Therefore, symbol timing recovery is one of the most crucial jobs of a digital communications receiver. In the days of analog clock recovery, a timing error detector provided the instant to sample the Rx waveform at 1 sample/symbol at the maximum eye opening. However, discrete-time processing opened the doors for better timing recovery schemes as an ever increasing number of transistors within the same area consistently keeps bringing the digital processing cost down. Consequently, the use of analog circuits to control the timing

Minimum distance rule based detector decisions in a QPSK constellation in the presence of a carrier frequency offset

June 6, 2016 DSP / Wireless/SDR

How a Frequency Locked Loop (FLL) Works

We saw before how a carrier frequency offset distorts the received signal. Later, we also described the classification of frequency synchronization techniques according to the availability of the symbol timing. Today, we will learn about the workings of a frequency locked loop. Background A Phase Locked Loop (PLL) is a device used to synchronize a periodic waveform with a reference periodic waveform. It is an automatic control system in which the phase of the output signal is locked to the phase of the input reference signal. In the article referred above, we also discussed that for a very small frequency